They are individually set to 1 when the corresponding sample is generated and the corresponding DA bit is already at 1, meaning the previous sample has been overwritten unread by the later generated new one, hence its value has been lost. The overrun bits are aut...
After the start condition (ST) a slave address is sent, once a slave acknowledge has been returned (SAK), an 8-bit sub-address will be transmitted (SUB): the 7 LSB represent the actual register address while the MSB has no meaning. The IF_ADD_INC bit in CTRL_REG2 (11h) enables ...
After the start condition (ST) a slave address is sent, once a slave acknowledge has been returned (SAK), an 8-bit sub-address will be transmitted (SUB): the 7 LSB represent the actual register address while the MSB has no meaning. The IF_ADD_INC bit in CTRL_REG2 (11h) enables ...
After the start condition (ST) a slave address is sent, once a slave acknowledge has been returned (SAK), an 8-bit sub-address will be transmitted (SUB): the 7 LSB represent the actual register address while the MSB has no meaning. The IF_ADD_INC bit in CTRL_REG2 (11h) enables ...