(SI/CK) Individually Enables Disables Outputs, Selectable CLK0, CLK0 or CLK1, CLK1 Inputs • Full Rail-to-Rail Common-Mode Input Range • Receiver Input Threshold: ±100 mV • Available in 32-Pin LQFP and VQFN Package • Fail-Safe I/O-Pins for VDD = 0 V (Power Down) 2 ...
(LVDS-, CML-, LVPECL-compatible) • Fully integrated PLL, configurable loop bandwidth: 100kHz to 3MHz • Single or mixed supply operation for level translation: 1.8V, 2.5V and 3.3V • Configurable GPIOs – Status signals – Up to four individual output enables – Output divider ...
Vdd while the voltage at OUTX is approximately equal to Vdd-Vlogic, where Vlogic is the product of resistor value R and current value I. Logic LOW is defined when the voltage at terminal OUTX is approximately equal to Vdd while the voltage at OUT is approximately equal to Vdd-Vlogic. ...
Now, let us consider the frequency divider, depicted in Figure 1. When the input is not applied to the clock ports of the latches, only the bias voltage is applied to the gate of the transistors M1 and M2, and the frequency divider works as a CML ring oscillator, with a self-...
re A1. D00 D01 D02 D03 VDD D00 M1 M2 M4 M3 Y0 X M7 M5 M6 VDD Y0 Y1 Y2 Y3 CML to CMOS D0 CLK 0 CLK90 VSS FigFuirgeuAre1A. C1.iCrciurciut iatnadndstsrturuccttuurree ddiiaaggrraammooffththee4:41:1MMUXU.X. WiWthitthhtihsicsicricrucuitit,,ffoouurr loww--ssppeeeeddp...
Table 24. Input Stage Setting Settings to Use Input Protocol PECL Driver VDD Level 3.3V 3.3V VDD_CLK Voltage 2.5V Differential + NMOS 1.8V PECL 2.5V Differential + PMOS LVDS N/A Differential + NMOS HCSL N/A Differential + PMOS CML 3.3V Differential + NMOS CML 2.5V Differential + NMOS ...
CML, 0.8V CML, 1.8V CML, 1.8V — Analog, Variable Analog, Variable 3.3V CHIP_TEST_MODE[4:0]_RESERVED 5 IPD Static Subtotal Digital Power VDDO_3P3 OTPC_VDD1P8 VDDO_MDIO VDDC (Programmable) Subtotal 30 —— 21 I 1I 1I 46 I 69 — PWR PWR PWR PWR — 3.3V — 3.3V 1.8V ...
Output Supply Voltage Input voltage, All Inputs, except XTAL_IN XTAL_IN Storage temperature Junction Temperature Moisture Saturation Level Conditions Symbol VDD VDDO VIN VIN TSTG TJ MSL Min -0.5 -0.5 -0.3 -0.5 -55 Typ Max Units 3.6 V 3.6 V VDD+0.3 V 1.8 V 150 oC 125 oC 3 Notes: ...
(VIN) -0.5 4.0 V LVCMOS Input/Output Voltage -0.5 4.0 V CML Input Voltage -0.5 (VDD+0.5) V CML Input Current -30 30 mA Junction Temperature 125 °C Storage Temperature Range Tstg -40 125 °C (1) "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur...
The divider range is 1 to 1023. Duty cycle correction may be enabled for the output. When the divider is used even clocks may not output CML. In a JESD204B/C system, one clock output is a device clock driven from the clock divider and the other paired clock is from the SYSREF ...