[Lecture Notes in Electrical Engineering] VLSI Design: Circuits, Systems and Applications Volume 469 || Design of Ultra-Low-Voltage Energy Efficient Hybrid Full Adder Circuitdoi:10.1007/978-981-10-7251-2_15Li, JieSankar, A RaviBeulet, P Augusta Sophy...
Monteiro, J., Oliveira, A.: Finite state machine decomposition for low power. In: Proc. ACM/IEEE Design Automation Conf., pp. 758–763 (June 1998) About this Chapter Title Design of Low Power FSM Using Verilog in VLSI Book Title Quality, Reliability, Security and Robustness in Heterogen...
[Lecture Notes in Electrical Engineering] VLSI Design: Circuits, Systems and Applications Volume 469 || A Novel MTCMOS-Based On-Chip Soft-Start Circuit for... J Li,AR Sankar,PAS Beulet 被引量: 0发表: 2018年 Design and optimization of multithreshold CMOS (MTCMOS) circuits Reducing power ...
In the current trend technology, where portable electronic devices are used in our day-to-day life, the development of the electronic circuits which consumes low power with optimum performance is critically required. Adder is one of the circuitry which i
J. Yuan, C. Svensson, New single-clock CMOS latches and flipflops with improved speed and power savings. IEEE J. Solid-State Circ.32(1), 62–69 Google Scholar N.H. Weste, D. Harris,CMOS VLSI Design: A Circuits and Systems Perspective(Pearson Publication, 2015) ...
The approach to design of circuits VLSI is consistently focused on unforeseeable discrepancies and extreme power constraints [23]. By adopting bio-inspired architecture of the framework, the hierarchic agent is proposed to track the NoC design process. It has hierarchical power surveillance, in which...
Babayan-Mashhadi S, Lotfi R (2014) Analysis and design of a low-voltage low-power double-tail comparator. IEEE Trans Very Large Scale Integr (VLSI) Syst 22(2):343–352 Google Scholar Khorami A, Sharifkhani M (2017) Excess power elimination in high resolution dynamic comparators. Microelec...
design has not been explicitly addressed so far. At the same time, it is a crucial measure of goodness for an algorithm. Indeed, a cipher optimized with respect to energy has wide applications, especially in constrained environments running on a tight power/energy budget such as medical ...
A PLD (200) includes a power management unit (PMU 210) that selectively implements one or more different power-reduction techniques in response to power configuration
Among the integrated process compensation techniques, the main one aims at reducing the supply voltage of fast circuits in order to reduce their power consumption while maintaining the specified operating frequency. The proposed design flow includes efficient methodologies to gather/sort on-chip process ...