The comparator design occupying less area and consuming lesser power is suitable for bank of comparators in CMOS image readouts. The proposed dynamic comparator eliminates the stacking issue related to the conventional comparator and reduces the offset noise further. The need for low-noise, low-...
This thesis presents a high gain, low noise and low power dynamic residue amplifier and a low power, low noise dynamic comparator designed in TSMC 28nm process for a two step Pipelined SAR-ADC. The cascoded integrator dynamic residue amplifier (CIDRA) achieves a gain of 30dB with THD of 47...
This paper comments on four works for the optimization of comparator design. Today, with the development of integrated circuits, the requirements for comparators about low power, low delay, few offset voltage, and low noise are highly desirable. Specifically, these works made progress in the conven...
Comparative Analysis of High Speed Comparator for A to D Converters In this paper dynamic comparator along with the output buffer stage has been introduced. The simulation is carried out in 130 and 90nm technologies. The supply voltage for 130nm is 1.3V and for 90nm is 0.9V. Different analy...
This thesis presents a high gain, low noise and low power dynamic residue amplifier and a low power, low noise dynamic comparator designed in TSMC 28nm process for a two step Pipelined SAR-ADC. The cascoded integrator dynamic residue amp... SP Astgimath 被引量: 4发表: 2012年 加载更多研究...
A low-glitch dynamic latch in the sub-ranging flash ADCs reduces kickback noise referred to the input of comparator by isolating the pre-amplifier from ... YJ Kim,KH Lee,MH Lee,... - 《Ieice Transactions on Electronics》 被引量: 12发表: 2009年 A sub-sampling 4-bit 1.056-GS/s flash...
It consumes 2.86 μW at 250kS/s and the figure of merit is 85.7 fJ/conversion-step. It shows that this work efficiently reduces 52% to 80% power consumption of the dynamic comparator at 500kS/s to 125kS/s. 展开 关键词: CMOS integrated circuits adaptive control analogue-digital conversion...
To minimize effect of bandgap noise, novel low pass filter associate with bandgap reference circuit, which provides highly filtered reference voltage and fast settling time, is implemented. Dynamically operating current limiter using decent current comparator limits output current. Threshold current of ...
A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface This paper presents a 100 kS/s, 1.3 μW, 9.3 ENOB successive approximation ADC with a time-domain comparator. The proposed time-domain comparator utilizes ... Seon-Kyoo,...
3a. The threshold voltages are tunable by the resistance in the comparator circuit. As a guideline, the threshold voltage will be set as low as possible for recognizing the weak signals during the slow motions, but also need to be much higher than the background noise to avoid the false ...