Time-based calibrationNonbinary schemeThis paper presents a nonbinary 2b/cycle SAR ADC structure with two assistant loop-unrolled comparators. By using the reset time of 2-bit comparators, the proposed structure achieves extra single bit conversion after normal 2-bit conversions, thus removing one ...
This enabled the use of a simple bidirectional single-side switching scheme to eliminate switching logic which further boosts speed and reduces switching power. An 8b prototype ADC achieves 45dB SNDR and a Nyquist FOM of 31.3fJ/conv-step at 350MS/s in 40nm CMOS. 展开 ...
A 7-bit single-channel loop-unrolled successive approximation register (SAR) analog-to-digital converter (ADC) with a sampling rate of 1.7 GS/s at a power consumption of 1.38 mW is presented. To prove the concept, the circuit was fabricated in a 22-nm fully depleted silicon-on-insulator ...