marceloboeira/logisim-7-segment-display-driver Star40 Code Issues Pull requests ➿ TTL-7447-like implementation for logisim drivercircuitlogisim UpdatedMar 16, 2024 Daynlight/CPU Star35 Code Issues Pull requests Explore the 🖥️ CPU diagram 📊 and assembler 🛠️ written in Python, designed...
Plexers->7-Segment Display Decoder Component changes: New FF layout The Shift Register will show you its internal bits even when set to serial load Right click on Pin, Edit Contents and set its value typing the decimal number Added Sel pin in Register Added Preset pin in Register and Coun...
Added support for scanning 7-segment display on FPGA-boards Added first support for the openFpga toolchain for the ecp5 famely Note that this is experimental for the moment, so use it at your own risk. Improved Chinese localization Changed language code fromcntozh. ...
742373-bit to 8-line decoder, latched input16---missing 742383-bit to 8-line decoder16OKOKold diagram 74244octal buffer20OKOKold diagram 74247BCD to 7-segment decoder16--OKpin layout missing 74259octal adressable D-type latch---missing 74273...
SevenSegDecoded = 7-segment reeks met externe decoder SevenSegScanningActiveLow = 7-segment reeks met active low segment select SevenSegScanningActiveHi = 7-segment reeks met active high segment select # # data/IOComponentTypes.java # data/ComponentMapParser.java # # ==> FpgaIoPin = # ==...
Plexers->7-Segment Display Decoder Component changes: New FF layout The Shift Register will show you its internal bits even when set to serial load Right click on Pin, Edit Contents and set its value typing the decimal number Added Sel pin in Register ...