A System for Logical Design of Custom CMOS VLSI Functional Blocks with Reduced Power Consumption We describe a CMOSLD system to automate the design of irregular logic circuits of CMOS library elements. The main criteria of circuits optimization are the area and the power consumption. This system ...
For IC designers it is a most useful work of reference and should not be missing from the shelves of any self respecting library. JOHN HATFIELD, Department of Electrical Engineering and Electronics, UMIST 展开 DOI: 10.1177/002072099503200113 ...
Their model (library/lef) needs to be picked during the synthesis. It is essential to use the exhaustive list of Black-Box modules in LEC setup as these are the modules which don’t require internal verification but their interface has to be exhaustively checked so as to confirm their ...
custom VLSIC designswitched transistorinput signals set sequenceThe relationship between energy consumption and switching activity of logic circuits built of CMOS-based gates from the library of custom VLSIC designing. The switching activity of the logic circuit, i.e., total number of switched ...
In an embodiment, a non-volatile memory has erasable blocks of memory cells. The one or more of the erasable blocks include a particular block to be identified by a particular group of logical block addresses corresponding to a predetermined group of sectors.Inventors...
Digital VLSILogical effort theoryArtificial neural networksLogic synthesisConfigurable standard cellASIC designStandard cell library is the backbone of modern day application specific integrated circuit (ASIC) design flow provided by electronic design automation (EDA) vendors worldwide. In these libraries, ...
Proposed stochastic logical effort (SLE) delay model captures delay variations.One-time cell library characterization and linear SLE equations are presented.A Monte Carlo timing yield estimator based on SLE, called ISLE, is built.SLE and ISLE are tested in the existence of inter- and intra-die ...