1. Many EDA companies provide tools to do the check. A logical equivalence check can be performed between any two representations of a design: RTL vs Netlist or Netlist vs Netlist. Fig. 1 Basic IC Design Flow The necessary inputs needed for the LEC are being discussed in the paper and ...
eInfochips White Paper | Introduction of logical equivalence check, flow setup, steps to debug it, and solutions to fix LEC.