%lv = load <8 x i32>, ptr %x, align 16diff --git a/llvm/test/Transforms/VectorCombine/X86/extract-binop-inseltpoison.ll b/llvm/test/Transforms/VectorCombine/X86/extract-binop-inseltpoison.llindex 3d69f15fc5f249..effd846e7e6336 100644--- a/llvm/test/Transforms/VectorCombine/X86/extract...
llvm / llvm-project Public Notifications Fork 12.2k Star 29.6k [DAG] SDPatternMatch - add m_ExtractSubVector / m_InsertSubVector matchers #118846 New issue Open Description RKSimon opened on Dec 5, 2024 Add SDPatternMatch matchers and unit test coverage for ISD::EXTRACT_SUBVECTOR and...
get(X86::VEXTRACTF64X4Zmri), X86::sub_ymm); case X86::MOV32ri64: { Register Reg = MIB.getReg(0); Register Reg32 = RI.getSubReg(Reg, X86::sub_32bit); 48 changes: 24 additions & 24 deletions 48 llvm/lib/Target/X86/X86ReplaceableInstrs.def Original file line numberDiff line ...
llvm-svn2git-monorepo.rules llvm-svn2git-remainder.rules llvm-svn2git.sh llvm_filter.py make-repos.sh migrate-downstream-fork.py project-list update-authormap.py update-repo.sh upload-all.sh zip-downstream-fork.pyBreadcrumbs llvm-git-migration / extract-author-ids.py Latest...
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. - [AArch64] Additional shuffle subvector-extract cost tests. NFC · Prakhar-Dixit/llvm-project@3ddc9f0
@llvm/pr-subscribers-mlir-linalg @llvm/pr-subscribers-mlir-tensor @llvm/pr-subscribers-mlir Author: ofri frishman (ofri-frishman) Changes Add a pattern that bubbles up tensor.extract_slice through tensor.expand_shape. This pattern enables tiling and fusing op chains which contain tensor.expand_...
VectorCombine.cpp +++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp @@ -666,10 +666,9 @@ bool VectorCombine::foldInsExtFNeg(Instruction &I) { m_ExtractElt(m_Value(SrcVec), m_SpecificInt(Index))) return false; + // TODO: We could handle this with a length-changing shuffle. aut...
372 changes: 189 additions & 183 deletions 372 llvm/lib/Target/X86/X86ISelLowering.cpp Original file line numberDiff line numberDiff line change @@ -4079,7 +4079,7 @@ static SDValue extractSubVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG,...
Port of LLVM to the MOS 6502 and related processors - [VectorCombine] isExtractExtractCheap - specify the extract/insert sh… · llvm-mos/llvm-mos@1878b94
Port of LLVM to the MOS 6502 and related processors - [DAG] Ensure extract_subvector(insert_subvector(x,y,c1),c2) --> extra… · llvm-mos/llvm-mos@73b255c