1350 — ps at FVCO_CLK 320 MHz — 600 — ps ± 4.47 — ± 5.97 % JCYC_SPLL JACC_SPLL DUNL TSPLL_LOCK PLL Period Jitter (RMS)3 PLL accumulated jitter over 1µs (RMS)3 Lock exit frequency tolerance Lock detector detection time4 — — 150 × 10-6 + 1075(1/FSPLL_REF) s 1...
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1350 — ps at FVCO_CLK 320 MHz — 600 — ps ± 4.47 — ± 5.97 % JCYC_SPLL JACC_SPLL DUNL TSPLL_LOCK PLL Period Jitter (RMS)3 PLL accumulated jitter over 1µs (RMS)3 Lock exit frequency tolerance Lock detector detection time4 — — 150 × 10-6 + 1075(1/FSPLL_REF) s 1...