EXPORT GPIO_TBL GPIO_TBL IF :DEF:USE_XXX DCD GPIOG,6,10,1; NCSPG6:AF10 DCD GPIOB,2,10,0; DQSPB2:AF10 DCD GPIOF,10,9,0; CLKPF10:AF9 DCD GPIOD,11,9,0; D0PD11:AF9 RevA ; DCD GPIOB,1,6,0; D0PB1:AF6 RevB
*clk_priv, uint32_t rate); struct spi_desc *spi; structgpio_desc *gpio_desc_device_id; structgpio_desc *gpiodesc_resetb; struct gpio_desc *gpio_desc_sync; } AD9361_InitParam typedef struct{ 1 change: 1 addition& 0 deletions 1 projects/ad9361/src/9361_conv.c ...
280 int32_t gpio_cal_sw2; /* cal-sw2-gpios */ 282 281 /* External LO clocks */ 283 282 uint32_t (*ad_rfpllext_recalc_rate)(structrefclk_scale *clk_priv); 284 - int32_t (*ad9361_rfpllext_round_rate)(struct refclk_scale*clk_priv, uint32_t rate); 285 -int...
CLK_CS, .flags = 0}; + /***//** * @brief main ***/ int main(void) { + int32_t status; #ifdef XILINX_PLATFORM Xil_ICacheEnable(); Xil_DCacheEnable(); @@ -375,8 +384,19 @@ int main(void) // NOTE: The user has to choose the GPIO numbers according to desired /...
{ struct spi_device *spi = phy->spi; uint32_t clktf, clkrf; int32_t txnco_word, rxnco_word, txnco_freq, ret; - uint8_t __rx_phase = 0, reg_inv_bits = 0, val, decim; - const uint8_t(*tab)[3]; - uint32_t index_max, i, lpf_tia_mask; + uint8_t __rx_phase...
device structure. * @param clk_delay_ - Enable or disable Mag/Phaseclock delay. * Accepted values true * false * @return0 in case of success negative error code otherwise. */ int32_t ad713x_mag_phase_delay(ad713x_dev *dev, bool clk_delay_en) { 32_t ret; ret = ...
Expand DownExpand Up@@ -439,7 +442,8 @@ int32_t gpio_set_value(gpio_desc *desc, pdata=Xil_In32(XPAR_PS7_GPIO_0_BASEADDR+0x02c8); Xil_Out32((XPAR_PS7_GPIO_0_BASEADDR+0x02c8), (pdata|pmask)); pdata=Xil_In32(XPAR_PS7_GPIO_0_BASEADDR+0x004c); ...