I/O port hardware register map (continued) Block Register label Register name Port G PG_ODR PG_IDR PG_DDR PG_CR1 PG_CR2 Port F data output latch register Port G input pin value register Port G data direction register Port G control register 1 Port G control register ...
I/O port hardware register map Block Register label Register name Port A Port B Port C PA_ODR PA_IDR PA_DDR PA_CR1 PA_CR2 PB_ODR PB_IDR PB_DDR PB_CR1 PB_CR2 PC_ODR PB_IDR PC_DDR PC_CR1 PC_CR2 Port A data output latch register Port A input pin value register Port A data ...
±0.25V, TA = 0˚C to 70˚C, IPI = 100 µA (Unless otherwise specified) (Continued) RSDS Output (CLKP/N, xyP/N;x=R,G,B;y=0,1,2), V DD = 2.25V to 2.75V (Unless otherwise specified) Symbol Parameter Conditions Min Typ Max Units |V ODRSDS| Differential Output Voltage ...
I/O port hardware register map (continued) Address Block Register label Register name 0x00 5019 0x00 501A 0x00 501B 0x00 501C 0x00 501D 0x00 501E 0x00 501F 0x00 5020 0x00 5021 0x00 5022 0x00 5023 to 0x00 502C Port F Port G PF_ODR PF_IDR PF_DDR PF_CR1 PF_CR2 PG_ODR ...
I/O port hardware register map (continued) Block Register label Register name Port F PF_ODR PF_IDR PF_DDR PF_CR1 PF_CR2 Port F data output latch register Port F input pin value register Port F data direction register Port F control register 1 Port F control register 2 Reset status 0x...
I/O port hardware register map (continued) Block Register label Register name Port G PG_ODR PG_IDR PG_DDR PG_CR1 PG_CR2 Port F data output latch register Port G input pin value register Port G data direction register Port G control register 1 Port G control register 2 Reserved area ...
I/O port hardware register map (continued) Block Register label Register name Port G PG_ODR PG_IDR PG_DDR PG_CR1 PG_CR2 Port F data output latch register Port G input pin value register Port G data direction register Port G control register 1 Port G control register 2 Reserved area (...
I/O port hardware register map (continued) Block Register label Register name Port G PG_ODR PG_IDR PG_DDR PG_CR1 PG_CR2 Port F data output latch register Port G input pin value register Port G data direction register Port G control register 1 Port G control register 2 Reserved area (...