vaK1zYiDw3xUolOV9kC2n++WAaw54yvYGM SB9csXxP51BHGFcfIwCnzR1sJ7baMlNODgjbLnpv/JiInEWsnk2J7B8hlpPD7Lx04tgpJ4V4vyoZ YU9+EARILV9erJoET7RA1dzhSg8hU/BxohYekBguAAX446qrLAov4MWneYsbHVMzPnZsU3VDqLhE 6LteQTX9GBwq/fp6gQyPtjeGeSTZdePJ9cmCSfglkdiCgmzo3oB9Ly3uZMeeDsDxhgp6uml3w7ds TGZn0...
TXRXSLVS on FPGA2.5 V2.5 V2.5 VSLVS peerZ0 = 50 ΩZ0 = 50 Ω48.7 Ω48.7 Ω221 Ω221 Ω15 Ω100 Ω15 Ω eJzMvVmTXsmRHfhOM/6HnIc2IzUGIPaFb0U0W8O25GLcRKpNRksCWSxIWEpYSJV+/YS7n+MRX36Z 1ZRmHjQ9KgIH94sbNxYPX457/NP/9evfPvvq9Ye/3D/Lz8PND3/wT//08uP93ecPH39yo/DNz9++ /fLp80...