不只是指令类型，几乎所有部分都调换了位置。主要做的事情就是合并和简化，毕竟RISC的R是Reduced的意思嘛。
CVA6 RISC-V CPU CVA6 is a 6-stage, single issue, in-order CPU which implements the 64-bit RISC-V instruction set. It fully implements I, M, A and C extensions as specified in Volume I: User-Level ISA V 2.3 as well as the draft privilege extension 1.10. It implements three privile...