mutex_lock(&pdata->plug_mutex);mask_irq(pdata->irq[HI6402_IRQ_BTNDOWN_COMP1],true);mask_irq(pdata->irq[HI6402_IRQ_BTNUP_COMP1],true);mask_irq(pdata->irq[HI6402_IRQ_BTNDOWN_ECO],true);/* todo */hi6402_reg_clr_bit(pdata->p_irq, HI6402_MICBIAS_ECO_REG,0); hi6402_reg_...
RestoreIRQMask(savedMask);return(DCL_HGPT_MAGIC_NUM | GPT1);//use return instead of break;caseGPT2:#if!defined(__IC_SLT__)// for slt load, always return a valid handlesavedMask =SaveAndSetIRQMask();if(KAL_TRUE == fgGPT2Open) { RestoreIRQMask(savedMask);returnDCL_HANDLE_INVALID; ...
irq_mask().Add check for the valid callback of irq_mask() and if it isthere then call it from irq_disable.This is based on change done by:sreenivasulu velpula <***@nvidia.com>Signed-off-by: sreenivasulu velpula <***@nvidia.com>...
irqc->irq_mask = irq_gc_mask_set_bit; irqc->irq_unmask = irq_gc_mask_clr_bit; This now causes boot failure on OMAP1 platforms, after commit 450fa54cfd66 ("gpio: omap: convert to use generic irq handler") which forces these callbacks to be called during GPIO IRQs mapping from gpi...
irq_ack = irq_gc_ack_set_bit; ct[i].chip.irq_mask = irq_gc_mask_disable_reg; ct[i].chip.irq_mask_ack = irq_gc_mask_disable_reg_and_ack; ct[i].chip.irq_mask_ack = irq_gc_mask_disable_and_ack_set; ct[i].chip.irq_unmask = irq_gc_unmask_enable_reg;...
内核cpumask_t,设置中断irq的cpu亲和性,打印可阅读的方式如下:比如在128核的cpu下面,有四个long类型,总共128。中断亲和性使用cpumask_t来表示。
Remove use of the deprecated mask_invert flag. Inverted mask registers (where a '1' bit enables an IRQ) can be described more directly as an unmask register. Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by...
Mask = (u8)(~(u8)(0x03U << (((u8)IrqNum % 4U) * 2U)));上述来自于stm8s_itc.c (...
> - DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST) > + DSI_IRQ_TA_TIMEOUT) > #define DSI_IRQ_CHANNEL_MASK 0xf > > /* Virtual channel interrupts */ > Thanks, queued for 4.5. Tomi Description:OpenPGP digital signature
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