(struct tdm_clock *)(TDM_CLKREG_OFFSET + (u8 *)priv->tdm_regs);/* irqs mapping for tdm err/dmac err, dmac done */priv->tdm_err_intr =irq_of_parse_and_map(ofdev->node,0);if(priv->tdm_err_intr == NO_IRQ) { ret = -EINVAL;gotoerr_tdmerr_irqmap; } priv->dmac_done_intr...
irq_of_parse_and_map的原理是当前实际的trigger和设备树的对比,然后分配中断号。我还以为直接从设备树获取呢?所以通过此代码我觉得设备树中我因为配置化为IRQ_TYPE_NONE。 另外一个问题,irq_free后怎么还有残留信息没有reset中断状态。导致再次加载读取当前type=3?暂时没有时间去分析源码。 四,小结 好吧,了解了这样...
The irq_of_parse_and_map() returns 0 on failure, not a negative ERRNO. Fixes: f48e699 ("irqchip/aspeed-i2c-ic: Add I2C IRQ controller for Aspeed") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore....
sirq =irq_of_parse_and_map(np,0);if(sirq == NO_IRQ)gotoend;/* Initialize the CPM interrupt controller. */hwirq = (unsignedint)virq_to_hw(sirq); out_be32(&cpic_reg->cpic_cicr, (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) | ((hwirq/2) <<13) |...