随着半导体制造工艺,EDA工具和VLSI设计技术的发展,集成电路速度越来越高,集成度越来越大.这种趋势导致电源/地线网(P/G网)上产生电压降(IR-drop).过大的电压降会导致电源电压波动,噪声容限减小,逻辑门延迟增加,开关速度降低,产生逻辑错误甚至逻辑功能失效.由于P/G网网络规模巨大,通用的电路模拟工具根本不可能完成对P/...
VLSIPG网的瞬态IRdrop分析的中期报告本次分析的目的是对VLSIPG网中的瞬态IRdrop进行建模和仿真分析,以评估电路的可靠性和处理电源噪声的能力。在初期的研究中,我们对VLSIPG网的物理结构进行了分析,包括功率分配网络、电源和地节点的布局等方面。根据这些结构特征,我们建立了电路模型并对其进行了仿真。仿真模型中包括了...
嵌套式层次化IR-drop求解的主要步骤为: 3 VLSI P/G网的瞬态IR—drop分析 1. 对最底层子网进行Cholesky分解,得到子网等效模型I=A*V中的A; 2. 由子网等效模型建立上一层等效全局网模型; 3.求解该全局网,得到端口节点电压; 4. 用适当的迭代法求解每个子网内部节点的电压; 5.对上～层子网进行从l～5的操作,...
Data mining and web-based reporting software for power, IR drop and EM analysis in VLSI designdoi:10.1109/ictus.2017.8286028Qing ZhuIEEEInternational Conference on Computer Communications
The new architecture cell is designed such that it takes same area as the conventional cell but provides more delay & has inherit decap cells also which further helps in reducing dynamic IR drop. Sometimes, there is a scenario where there is no space to add decap cells and a concern for...
Due to aggressive technology node scaling, resistance of back-end-of-line (BEOL) layers increases dramatically in sub-10nm VLSI, causing high supply voltage (IR) drop. To solve this problem, pre-placed or post-placed power staples are inserted in pin-access layers to connect adjacent power ...