这两个引脚的功能是相似的,都是用来控制在Configuration完成之前,所有普通IO的上拉电阻是否使能的。对应到图 1中,即Output Buffer输出高阻,Input Buffer对外始终为高阻,此时选择是否连接上拉电阻。 实际的物理引脚举例:xc7z020-484 K16 IO_L3P_T0_DQS_PUDC_B_34 xc7z010clg400-1 IO_L3P_TO_DQS_PUDC_B_34 需...
PUDCPUDC#JX1,pin17Bank34,U13IO_L3P_T0_DQS_PUDC_B_34 DONE_LEDFPGA_DONEJX1,pin8Bank0,R11DONE_0 CARRIER_SRST#CARRIER_SRST#JX1,pin6--- PWR_ENPWR_ENJX1,pin5--- JTAG_TDOJTAG_TDOJX1,pin3Bank0,F6TDO_0 JTAG_TDIJTAG_TDIJX1,pin4Bank0,G6TDI_0 JTAG_TMSJTAG_TMSJX1,pin2Bank0,J6...