12:46:39.679 -> [ 707][E][esp32-hal-gpio.c:95] __pinMode(): Invalid pin selected 12:46:39.679 -> E (271) gpio: gpio_set_level(226): GPIO output gpio_num error 12:46:39.679 -> [ 707][E][esp32-hal-spi.c:208] spiAttachMISO(): HSPI Does not have default pins on ESP...
They all defaulted to double-sync on RX GPIO pin assignment. Interestingly, the PSoC4 SCB based UART component performs synchronization within the component and the GPIO is set to transparent. Like Reply 392 0 moxirex Level 2 30 Dec 2024 It seems like a timing...
The generated code in the pin config shows inputBuffer as PORT_INPUT_BUFFER_NOT_AVAILABLE, which means the IMCR does not get set to the correct value during Siul2_Ip_PortInit() { .base = IP_SIUL2, .pinPortIdx = 29u, .mux = PORT_MUX_AS_GPIO, .safeMode = PORT_SAFE_MODE_NOT_AVA...
Given some of the examples which show a failure after a number of seconds on a device by just using timer interrupts and GPIO toggles, i.e. without any dependencies on external inputs, do TI have the ability to run a cycle-ac...
In particular, the south bridge 526 may provide one or more universal serial bus (“USB”) ports 532, an Ethernet controller 560, and one or more general purpose input/output (“GPIO”) pins 534. The south bridge 526 may also provide a bus for interfacing peripheral card devices such as...
They all defaulted to double-sync on RX GPIO pin assignment. Interestingly, the PSoC4 SCB based UART component performs synchronization within the component and the GPIO is set to transparent. Like 456 0 moxirex Level 2 30 Dec 2024 It seems like a timing or c...