Access time and cycle time, measured at the storage card, are 125 nsec and 400 nsec, respectively. The array module contains four chips or 512 bits. It is a stacked, two substrate module with two chips per substrate. III. Arithmetic Indicators ...
A buffer 46 applies address signals received via an address bus to a device selection 48 which generates a separate peripheral enable signal for each peripheral device logic block on the APCP board 5. Only one peripheral device may be enabled for a data cycle on data bus 1 40 or data bus...