There is a vector A(7 down to 0).Now we have to add this vector with an integer(let it be 5).B(7 down to 0) is output.Then how to write the vhdl
I was unable to find a mention of it in the documentation. There is no connection to it in the sample declaration in the _inst.vhd file which the wizard generated. I chose all the default options and didn't change anything. I opted to not have a clock enable or ...
But we need to see the declaration of A and B to see what code you really need. Translate 0 Kudos Copy link Reply Altera_Forum Honored Contributor II 11-22-2012 09:19 AM 6,757 Views I have written the code as below: Library IEEE; use IEEE.std_lo...
But we need to see the declaration of A and B to see what code you really need. Translate 0 Kudos Copy link Reply Altera_Forum Honored Contributor II 11-22-2012 09:19 AM 6,741 Views I have written the code as below: Library IEEE; use IEEE.std_lo...