57549 - Vivado Simulator - "[VRFC 10-1089] near character ‘0’ ; 3 visible types match here" when directly instantiating Verilog modules in VHDL Description I am directly instantiating Verilog modules in VHDL similar to the following:
Also If I wanted to create one and use it in my program how do I include it in my verilog design file library. Do I need to go to a menu and include the file so it knows where it is? Ive been trying to find this for a while but not sure what to search for and wha...