Also note that a ratio of the first frequency to the second frequency is greater than or equal to one.doi:US20100085123 A1FRANS, YohanLEE, Hae-changKIM, JaehaUSUS20100085123 Oct 9, 2009 Apr 8, 2010 Rambus Inc. Injection-locked clock multiplier...
An injection-locked clock multiplier (ILCM) is considered to be a promising solution that can generate low-jitter, high-frequency clocks, using a limited b... S Choi,S Yoo,J Choi - IEEE International Solid-state Circuits Conference 被引量: 10发表: 2016年 A 130-nm CMOS 0.007- Ring-Oscil...
The reference path circuit may include an injection locked multiplier (ILM) and a group of one or more buffer amplifiers. The ILM may receive a sinusoidal reference signal from a reference oscillator at a reference frequency. The ILM may generate a sinusoidal ILM output signal at an ILM output...
Moreover, recently, PLLs with an injection-locked frequency divider and frequency multiplier, and a clock and data recovery circuit (CDR) were presented. This paper describes a study on a ring-VCO-based PLL with pulse injection locking as a potential solution to realize a scalable inductorless ...
With its high tunability, simple and robust all-fibre implementation, and low excess noise, the demonstrated RRM system may find diverse applications in microwave photonics, optical communications, photonic analogue-to-digital conversion, and clock distribution networks....
The reference signal is then repeatedly delayed by the minimum delay of which the delay line is capable (delay 0) every even clock cycle and by a predetermined delay every odd clock cycle (delay N). The flip-flop can be considered an early-late detector. If the oscillator is late ...
This paper presents a 20GHz subharmonic injection-locked clock multiplier (SILCM), which adopts a mixer based self-align injection timing control loop to guarantee the optimal injection point. In addition, to further improve the injection time accuracy and reduce the super, a V/I mismatch ...
This paper presents an injection-locked clock multiplier (ILCM) with a digital self-alignment frequency tracking loop (SA-FTL) to reduce the reference spur by calibrating the frequency mismatch and delay offset. To improve the power efficiency, the SA-FTL detects errors in low frequency, where ...
This paper presents a simple injection-locked all-digital clock multiplier (ADCM) can generate multiple clock signals from a single reference signal. The example uses in this paper is a 2X multiplier. Howevfer, the ADCM is capable of generating other frequencies, such as 3X, and 4X.CHAN ...
The clock multiplier was designed with the prototype \\Delta\\Sigma PLL in the 65-nm CMOS process. It can provide five reference frequencies, i.e., 19.2, 28.8, 48, 57.6, and 96 MHz. The phase noise of the 96-MHz signal was -130.0 and -131.8 dBc/Hz at 100 kHz and 1 MHz offset...