initreg用法分为两步:编译选项为 +vcs+initreg+random 仿真选项为 +vcs+initreg+0//intialize to value 0+vcs+initreg+1//initialize to value 1 +vcs+initreg+x //intialize to value x +vcs+initreg+z //initialize to value z +vcs+initreg+random //initialize to value 0 or 1 with default random ...
hisi-initregtable-parser Make them binary blobs human readable. Build: gcc -Wall -g hisi-initregtable-parser.c -o hisi-initregtable-parser Parses HiSilicon SoC register tables(in binary format) used in bootloader(u-boot) with early low level function: init_registers(uint32_t* table_start_ad...
class PhaseInitReg() extends PhaseNetlist { override def impl(pc: PhaseContext): Unit = { import pc._SpinalProgress("Initialize all registers not initialized")walkComponents{ comp => comp.rework{ comp.dslBody.walkStatements{case bt: BaseType if bt.isReg =>SpinalInfo(s"Init register ${bt.to...