/*#define SYSCLK_FREQ_HSE HSE_VALUE */ /*#define SYSCLK_FREQ_24MHz 24000000 */ /*#de...
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)...
junan@ZEN2:/lib/modules/5.19.0-50-generic/kernel/drivers/char$ ls agp applicom.ko hangcheck-timer.ko hw_random ipmi lp.ko mwave nvram.ko pcmcia ppdev.ko tlclk.ko tpm uv_mmtimer.ko xillybus junan@ZEN2:/lib/modules/5.19.0-50-generic/kernel/drivers/char$ file lp.ko lp.ko: ELF 64-b...
If you're working in a POSIX environment, the script gethz.sh will compile and run a simple program that determines the value of the _SC_CLK_TCK parameter which corresponds to the number of clock "ticks" per second as configured in the kernel. This information can also be retrieved by ...
__HAL_RCC_BKPSRAM_CLK_ENABLE();/* Compute the prescaler value to have TIM3 counter clock equal to 10 KHz */ uwPrescalerValue = (uint32_t) ((SystemCoreClock /2) / 10000) - 1;/* Set TIMx instance */ TimHandle.Instance = TIM3;/* Initialize TIM3 peripheral as follows:+...
KEEP(*(SORT(___kentry+*))) *(.init.data init.data.*) *(.meminit.data*) *(.init.rodata .init.rodata.*) *(.meminit.rodata) . = ALIGN(8); __clk_of_table = .; KEEP(*(__clk_of_table)) KEEP(*(__clk_of_table_end)) . = ALIGN(8); __reservedmem_of_table = .; KE...
ddrphy_init_set_dfi_clk(initial_drate); /* D-aasert the presetn */ reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); /* Step2: Program the dwc_ddr_umctl2 registers */ debug("DDRINFO: ddrc config start\n"); ddr_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); ...
set_cpu_clk_info, /* Setup clock information */ #endif #ifdef CONFIG_EFI_LOADER efi_memory_init, #endif stdio_init_tables, initr_serial, initr_announce, INIT_FUNC_WATCHDOG_RESET #ifdef CONFIG_NEEDS_MANUAL_RELOC initr_manual_reloc_cmdtable, ...
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 0; // Return ADC clock to original state EDIS; // CLKIN = OSCCLK x 12 / 2 if(!SysCtrlRegs.PLLSTS.bit.MCLKSTS){ // Device is not in limp mode if(SysCtrlRegs.PLLCR.bit.DIV != 12){
RCC_ADCCLKConfig(RCC_PCLK2_Div6);/* Enable DMA clock */ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_...