In some way, this is a diff tool, but it takes into account the Tarmac trace format and the structure of the executed code. The command line syntax looks like: paf-constanttime [ options ] FUNCTION TRACEFILE... The following options are recognized: --ignore-conditional-execution-differences...
Simulator supports IEEE 1364-2001 std for verilog, OVI 2.0, and verilog XL. System Verilog extensions to verilog as defined in IEEE P1800 std also implemented. We use compiler (ncvlog) and than elaborator (ncelab), which are integrated into IES. When we compile and elaborate a design, all...