Implementation of all-optical NAND logic gate and half-adder using the micro-ring resonator structuresMicro-ring resonatorAll optical NAND gateAll optical half adderThe computation of digital combinational and sequential logic functionality in the optical domain is one of the most important aspects, ...
A family of full-custom conventional CMOS Logic and an Adiabatic Logic units for example, an inverter, a two-input NAND gate, a two-input NOR gate, a two- input XOR gate a two-to-one multiplexer and a one- bit Full Adder were designed in Mentor Graphics IC Design Architect using ...
(3,2) blocks, we must still address the issue of how to implement the (3,2) block (carry save adder) efficiently. Functionally, the carry save adder is identical to the full adder. The full adder is usually implemented with a reduced delay from C in to C out because the carry chain...
The PWM and SAR logic are synthesizable and parametrizable, using a low number of resources, in order to be portable for low-cost FPGA families. The methodology and PWM optimizations are tested on a Zynq-7000 device from Xilinx; however, they can be adapted to any other FPGA. Keywords: ...
The PWM and SAR logic are synthesizable and parametrizable, using a low number of resources, in order to be portable for low-cost FPGA families. The methodology and PWM optimizations are tested on a Zynq-7000 device from Xilinx; however, they can be adapted to any other FPGA. Keywords: ...
We solve the function expressions in every segment between piecewise points using the least squares method. We then compare the absolute errors of different fitting function with potential piecewise points and choose a single function expression as the hardware implementation scheme to achieve higher ...
Therefore, in this paper, we propose a master–slave AMR architecture using the reconfigurability of field-programmable gate arrays (FPGAs). First, we discuss the method of building AMR, by using a stack convolution autoencoder (CAE), and analyze the principles of training and classification. ...
Journal of Imaging Article Memory Efficient VLSI Implementation of Real-Time Motion Detection System Using FPGA Platform Sanjay Singh 1,2,*, Atanendu Sekhar Mandal 1,2, Chandra Shekhar 1,2 and Anil Vohra 3 1 CSIR—Central Electronics Engineering Research Institute (CSIR-CEERI), Pilani 333031, ...
the NOT gate circuit in FPGA. Finally, the adder is designed by using the logic gates. Compared with traditional CMOS circuits, the memristor-based logic circuit can not only increase the density of the device, but also reduce the power consumption and improve the operation speed of the ...