Implementation of all-optical NAND logic gate and half-adder using the micro-ring resonator structuresMicro-ring resonatorAll optical NAND gateAll optical half adderThe computation of digital combinational and
A family of full-custom conventional CMOS Logic and an Adiabatic Logic units for example, an inverter, a two-input NAND gate, a two-input NOR gate, a two- input XOR gate a two-to-one multiplexer and a one- bit Full Adder were designed in Mentor Graphics IC Design Architect using ...
Erratum to “Method of implementation of frequency encoded all optical half adder, half subtractor and full adder based on semiconductor optical amplifiers and add drop multiplexers” [Optik, in press] Optik, Volume 122, Issue 20, October 2011, Pages 1843 Kousik MukherjeeView PDF Abstract A novel...
Carry Save Adder Implementation December 11, 2004 page 2 of 10 In both cases, we see the functions have 1. Common sub-functions 2. The common part is gated by a complementary input. These two properties allow the transistors for the common part to be shared. Consider full ...
Multiple-input multiple-output (MIMO) technology in com- bination with orthogonal frequency-division multiplexing (OFDM) is the key to meet the demands for data rate and link reliability of modern wide- band wireless communication systems, such as IEEE 802.11n or 3GPP- LTE. The full potential ...
In an embodiment, a method to automatically select groups of signals to be multiplexed on pins of a programmable logic device in a programmable logic device implementation of at lea
Journal of Imaging Article Memory Efficient VLSI Implementation of Real-Time Motion Detection System Using FPGA Platform Sanjay Singh 1,2,*, Atanendu Sekhar Mandal 1,2, Chandra Shekhar 1,2 and Anil Vohra 3 1 CSIR—Central Electronics Engineering Research Institute (CSIR-CEERI), Pilani 333031, ...
The evaluation of the proposed approach is performed through the design of an X-MRL-based full adder. The design is presented with its layout and corresponding simulation results using the Cadence Virtuoso toolset and CMOS 6565nm process. The comparison with a pure CMOS implementation is promising...
However, this solution uses instances to the library of the CMOS technology in order to permit the filter implementation by using the automatic translation tools. This way, the R of the filter is implemented on the high-resistivity polysilicon layer, and the C by using the metal–insulation–...
We solve the function expressions in every segment between piecewise points using the least squares method. We then compare the absolute errors of different fitting function with potential piecewise points and choose a single function expression as the hardware implementation scheme to achieve higher ...