modulemy_des (my_if _if);always@(posedge_if.clk)beginif(_if.push)begin// Immediate assertion and ensures that fifo is not full when push is 1a_push:assert(!_if.full)begin$display("push when fifo not full !");endelsebegin$display("[FAIL] push when fifo full !");endendif(_if.po...
SystemVerilog Assertions module asertion_ex; bit clk,a,b; //clock generation always #5 clk = ~clk; //generating 'a' initial begin a=1; b=1; #15 b=0; #10 b=1; a=0; #20 a=1; #10; $finish; end //Immediate assertion always @(posedge clk) assert (a && b); endmodule ...