When LATCHINPUTVALUE is enabled, puts the PLL into low-power mode; PLL output held static at last input clock value. iCEGate To save power, the optional iCEGate latch can selectively freeze the state of individual, non-registered inputs within an I/O bank. Registered inputs are effect...
LATCHINPUTVALUE Input When enabled, puts the PLL into low-power mode; PLL output is held static at the last input clock value. Set ENABLE ICEGATE_PORTA and PORTB to ‘1’ to enable. PLLOUTGLOBAL Output Output from the Phase-Locked Loop (PLL). Drives a global clock network on the FPGA...
http://machine-name/ICEGate/Category/Service If the URL for the new service is not known, a list of the available services may be determined from the Cool ICE system by specifying the Cool ICE URL as follows: http;://machine-name/ICEGate This call will result in a presentation of a men...
Table 2-9. iCE40 Power Saving Features Description Device Subsystem PLL iCEGate Feature Description When LATCHINPUTVALUE is enabled, forces the PLL into low-power mode; PLL output held static at last input clock value. To save power, the optional iCEgate latch can selectively freeze the state ...