24 changes: 24 additions & 0 deletions 24 2019/2019_grad_cell/.synopsys_dc.setup Original file line numberDiff line numberDiff line change @@ -0,0 +1,24 @@ set company "CIC" set designer "Student" set search_path "/home/cell_library/CBDK_IC_Contest_v2.5/SynopsysDC/db/ $search_...
IC Design Contest Cell-Based Resources Readme Activity Stars 0 stars Watchers 0 watching Forks 0 forks Report repository Releases No releases published Packages No packages published Languages Verilog 97.8% Jupyter Notebook 1.1% SystemVerilog 0.5% Tcl 0.2% Batchfile 0.2% Shell ...
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() ictsc-rikka-rikka-1 | /go/pkg/mod/github.com/gin-gonic/gin@v1.7.2/context.go:165 (0xbe1df8) ictsc-rikka-rikka-1 | (*Context).Next: c.handlers[c.index](c) ictsc-rikka-rikka-1 | /go/pkg/mod/github.com/zsais/go-gin-prometheus@v0.1.0/middleware.go:364 (0xbe1dd8) ic...