Hello,I am wondering if the phase relation between the ODIV output of the IBUFDS_GTE and its input is deterministic or if there is a configuration to have it deterministic? Same question for BUFG_GT, does the O output of the BUFG_GT has a d
While building an OOC module in Vivado using the HD flow, I'm getting this DRC violation and can't find any information about it. ERROR: [Drc 23-20] Rule violation (REQP-1619) IBUFDS_GTE2_driven_by_IBUF - IBUFDS_GTE2 refclk_ibuf pins I and IB should be driven by IBUFs. Looking...
69021 - JESD204 - 2017.1 - UltraScale / UltraScale+ IBUFDS_GTE output instability Description When using the JESD204 core and PHY with clock configuration using the refclk as the core clock, clock output instability from the IBUFDS_GTE might be seen. ...
I found something strange recently using IBUFDS_GTE4. Device: Zynq UltraScale\+ MPSoC Shown in the figure, I use this way to drive my JESD204 core_clk , which is driven by IBUFDS_GTE4.ODIV2. And also the core_clk was set as debug core domain in my project. It succeed ...
[DRC 23-20] Rule violation (PDCN-2721) IBUFDS_GT_loads_clock_region - IBUFDS_GTE2 IBUFDS_GTE2_inst drives MMCME2_ADV cpu_ref_pll_inst/inst/mmcm_adv_inst in a different clock region and must do so using local routing resources which...
I've just upgraded to 2015.3 from 2015.1 and have started to recieve the error message below when trying to generate a bitstream. [DRC 23-20] Rule violation (PDCN-2721) IBUFDS_GT_loads_clock_region - IBUFDS_GTE2 IBU
[DRC 23-20] Rule violation (PDCN-2721) IBUFDS_GT_loads_clock_region - IBUFDS_GTE2 IBUFDS_GTE2_inst drives MMCME2_ADV cpu_ref_pll_inst/inst/mmcm_adv_inst in a different clock region and must do so using local routing resources w...