I2C总线使用流程: 1. 配置I2C使能寄存器EN中关闭I2C使能; 2. 配置标准速度I2C时钟高电平寄存器SS_SCL_HCNT; 3. 配置标准速度I2C时钟低电平寄存器Uboot关于i2c和EEPROM的命令 0x50,因此完整命令为: [cpp] view plain copy i2c md 0x50 0.0 结果如下: 和预想的数据一样,打印出了eeprom的头信息。 i2c mm...
writel(lcnt, &i2c_base->ic_ss_scl_lcnt); @@ -113,8 +114,8 @@ static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base, hcnt = scl_sda_cfg->fs_hcnt; lcnt = scl_sda_cfg->fs_lcnt; } else { hcnt = (bus_mhz * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;...
tf 112 SCL fall time — 300 20 × (Vdd / 5.5) 113 300 ns tr 112 SDA rise time — 1000 20 300 ns tf 112 SDA fall time — 300 20 × (Vdd / 5.5) 113 300 ns Figure 16. I2C Timing Diagram 102 You can adjust Tclkhigh using the ic_ss_scl_hcnt or ic_fs_scl_hcnt register...
ic_ss_scl_lcnt This register sets the SCL clock low-period count for standard speed ic_fs_scl_hcnt This register sets the SCL clock high-period count for fast speed ic_fs_scl_lcnt This register sets the SCL clock low period count ic_intr_stat Each bit in this register has a cor...
[ 14.220957] i2c_designware 80860F41:01: DW_IC_SS_SCL_HCNT: 0x214 [ 14.228295] i2c_designware 80860F41:01: DW_IC_SS_SCL_LCNT: 0x272 [ 14.235592] i2c_designware 80860F41:01: DW_IC_FS_SCL_HCNT: 0x50 [ 14.242811] i2c_designware 80860F41:01: DW_IC_FS_SCL_LCNT: 0xad [ 14.25...
1.10a Dec 2009 Corrected dependencies for IC_SS_SCL_HIGH_COUNT, IC_SS_SCL_LOW_COUNT, IC_FS_SCL_HIGH_COUNT, and IC_FS_SCL_LOW_COUNT parameters; corrected IC_RE T_EN parameter description; modified description of IC_SDA_SETUP register; updated databook to new template for consistency with...
> > >>>DW_IC_SS_SCL_HCNT > > >>>and DW_IC_SS_SCL_LCNT registers. > > >There is a way to pass *CNT values already from ACPI to the driver -- It > > >looks for method called FMCN (or SSCN) and retrieves the values from ...
>i2c_dw_init() to calculate the values to program into the DW_IC_SS_SCL_HCNT >and DW_IC_SS_SCL_LCNT registers. There is a way to pass *CNT values already from ACPI to the driver -- It looks for method called FMCN (or SSCN) and retrieves the values from ...
Only ; after the SCL line has returned to its LOW state is the SDA state allowed to ; change. This is demonstrated in the diagram below. ; Note that I2C has 'open drain' communication electronics. SPI format, which ; requires 4 wires and is faster, has 'push-pull' communication ...
[OMAP_I2C_CNT_REG]=0x98, [OMAP_I2C_DATA_REG]=0x9c, [OMAP_I2C_SYSC_REG]=0x20, [OMAP_I2C_CON_REG]=0xa4, [OMAP_I2C_OA_REG]=0xa8, [OMAP_I2C_SA_REG]=0xac, [OMAP_I2C_PSC_REG]=0xb0, [OMAP_I2C_SCLL_REG]=0xb4, [OMAP_I2C_SCLH_REG]=0xb8, ...