i2c_slave_axil_master module 带有参数化 AXI lite 接口的 I2C 从模块。i2c_slave_wbm module 带有可...
I2C slaver 从机 Verilog代码实现 评分: 实现I2C从机的Verilog代码,简洁,且有注解,有利于帮助理解和实现。 I2C slaver 从机 Verilog 2013-03-10 上传 大小:6KB 所需: 50积分/C币 立即下载 i2c slave端verilog代码 salve端的i2c verilog代码,用于fpga。
The design is also synthesized in Xilinx XST 14.1. This module acts as a slave for the microprocessor which can be customized for no data loss.Keywords: Inter Integrated circuit, serial data, serial clock, slave, verilogDeepa KaithDr. Janankkumar B. PatelMr. Neeraj Gupta...
i2c_verilog范例
SPI总线提供一个MHz级的同步串行连接。由于要求嵌入式系统支持不断增长的协议和接口,针对常用协议的桥接设计为此提供了削减开发时间和成本的解决方案。这个参考设计实现了SPI master到I2C slave的桥接。用作为微控制器的标准I2C总线和SPI总线间的接口。使得微控制器可以直接通过其I2C总线与SPI总线进行通信。
Code README MIT license Verilog I2C interface For more information and updates:http://alexforencich.com/wiki/en/verilog/i2c/start GitHub repository:https://github.com/alexforencich/verilog-i2c Introduction I2C interface components. Includes full MyHDL testbench with intelligent bus cosimulation endp...
i2c_master.v i2c_master_axil.v i2c_master_wbs_16.v i2c_master_wbs_8.v i2c_single_reg.v i2c_slave.v i2c_slave_axil_master.v i2c_slave_wbm.v tb .gitignore AUTHORS COPYING README README.md verilog-i2c /rtl / i2c_master.v
实际结果可能取决于所选择的参数、时序约束和所用的器件。若要了解更详细的情况,请查阅设计文件。除非另有说明,所有的代码和设计工作都是在PC平台上完成的。 文档 技术资源 Reference Design 标题编号版本日期格式文件大小 a选择全部 aaI2C Slave Controller - Source Code RD11401.12/12/2015ZIP338.6 KB...
SmartDV's I2C Slave IP contains following. The I2C Slave interface is available in Source and netlist products. The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided. Easy to use Verilog Test Environment with Verilog Testcases ...
Synthesizable System Verilog source code or targeted FPGA netlist Testbench and sample test cases Simulation and Synthesis scripts Documentation I2CSPI-CTRL BRIEF (ALTERA) I2CSPI-CTRL BRIEF (AMD) Related Products I2C-MS I2C Master/Slave Controller I2C-SMBUS I2C & SMBus Controller SPI-MS ...