• JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16 • Driver strength selected by EMRS • On chip DLL align DQ, DQS and DQS transition with CK transition • DM masks write data-in at the both rising and falling • Dynamic On Die Termination supported •...
• DDR3 SDRAM Package : JEDEC standard 82ball FBGA(x4/x8) , 100ball FBGA(x16) with support balls • On chip DLL align DQ, DQS and /DQS transition with CK transition • Driver strength selected by EMRS • Dynamic On Die Termination supported • Asynchronous RESET pin suppo...
• JEDEC standard 78ball FBGA(x8), 96ball FBGA(x16) • Driver strength selected by EMRS • Dynamic On Die Termination supported • Asynchronous RESET pin supported • ZQ calibration supported • All addresses and control inputs except data, data strobes and data masks latched...
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. Absolute value of CCK-CCK. 5. Absolute value of CIO(DQS)-CIO(DQS). 6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE. 7. CDI_CTR applies to ODT, CS an...
JEDEC standard 78ball FBGA(x4/x8) Driver strength selected by EMRS Dynamic On Die Termination supported Asynchronous RESET pin supported ZQ calibration supported On chip DLL align DQ, DQS and DQS transition with CK transition • • DM masks write data-in at the both rising ...
• JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16 • Driver strength selected by EMRS • On chip DLL align DQ, DQS and DQS transition with CK transition • DM masks write data-in at the both rising and falling • Dynamic On Die Termination supported •...
• JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16 • Driver strength selected by EMRS • On chip DLL align DQ, DQS and DQS transition with CK transition • DM masks write data-in at the both rising and falling • Dynamic On Die Termination supported •...
• JEDEC standard 78ball FBGA(x4/x8) • Driver strength selected by EMRS • Dynamic On Die Termination supported • Asynchronous RESET pin supported • ZQ calibration supported • DM masks write data-in at the both rising and falling edges of the data strobe • All...
• DDR3 SDRAM Package : JEDEC standard 82ball FBGA(x4/x8) , 100ball FBGA(x16) with support balls • On chip DLL align DQ, DQS and /DQS transition with CK transition • Driver strength selected by EMRS • Dynamic On Die Termination supported • Asynchronous RESET pin suppo...
Ball Grid Array(FBGA) packages on a 240 pin glass-epoxy substrate. This DDR3 Unbuffered DIMM series based on 2Gb M ver. provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition. 1.1 Device Features ...