RegsRegsAuthenticator(MGF1, HMAC)Authentication &Cryptographic LayerControl & StatusRegister LayerHDCP Register Port(Avalon-MM)Repeater Message Port(Avalon-MM)HDCPKey PortHDCP CipherVideo & AuxControl & Status PortVideo Stream andAuxiliary LayerVideo & Aux DataOutput PortVideo & Aux DataInput PortAES...
÷C2÷C3÷C4÷C7÷C1÷MPLL Output MultiplexerCascade Output toAdjacent I/O PLLLVDS RX/TX ClockProgrammable clock routingFBOUTFBINLVDS Clock NetworkDedicated clock inputsfrom the same I/O bankProgrammable clock routingcascade input from I/O PLLin the same I/O columnor dedicated clock Inputsfrom...
MemoryControllerClock PhaseAlignmentSequencerPLLTo / From Other Sub-bankSub-bankTo / FromFPGA CoreTo / From Other Sub-bankI/O Lane 3I/O Lane 2I/O Lane 1I/O Lane 0TopSub-bankI/O BankBottom Sub-bankFabricFeedingI/O PLLOutput PathOutput PathInput PathOutput PathInput PathOutput PathInput ...