Hi, There is no eye mask requirement for the LVDS interface. What we do have is the LVDS IO specifications that can be found in device datasheet. For
I intend to use the I350 as a bridge in the following configuration: PCIe x1 on one side and 4 SGMII channels on the other. Is this feasible? Additionally, I'm unclear about the PCIe function. I couldn't find specific information about its function. ...
I am currently working with bsp41 and attempting to configure GMAC0 to operate in SGMII mode on the S32G-RDB3 board. Based on the RDB3 Ethernet Enablement Guide, I understand that I need to configure the following: GMAC0: SGMII PFE_MAC0, PFE_MAC1, PFE_MAC2: SGMII, SGMII, and RGMII...
Solved: Hello, If I configure GMAC0 and PFE_MAC1 to use SGMII (1G), does that mean both interfaces will utilize SerDes pins for external
But they also design it MAC_to_MAC, that means we use I350 in SGMII mode but we don't use a PHY。 At first, driver probe would error return -2. And I change some code in PHYID process, the eth device can be created。 I want to set force link, force s...
But they also design it MAC_to_MAC, that means we use I350 in SGMII mode but we don't use a PHY。 At first, driver probe would error return -2. And I change some code in PHYID process, the eth device can be created。 I want to set force link, force...
In the above block diagram, nic0 and nic1 are two SGMII interfaces where nic0 is externally connected to PHY and nic1 is a MAC to MAC interface without an external PHY. nic0 is working fine while nic1 is not working with the below DTS configurations: &pfe { status = "okay"; #ad...
Hi all: I have a question to ask you for advice.I'll be configure P1010 eTSEC1 and eTSEC2 and eTSEC3 to sgmii mode,eTSEC1 is worked ok
Hello, I am using Slimbootloader with FSP MR5, the PseTSN1 is using SGMII to connect a switch ASIC and we want the speed to 2.5G, the FSP setting
I am using Slimbootloader with FSP MR5, the PseTSN1 is using SGMII to connect a switch ASIC and we want the speed to 2.5G, the FSP setting "PseTsnGbePhyInterfaceType[1]" is set to 0x3 which means SGMII+, but we only get the sgmii bus running on 1G, and the ...