High-k gate stacks for planar, scaled CMOS integrated circuits, Microelectronic Engineering 69 - Brown, Zeitzoff, et al. - 2003H. R. Huff, A. Hou, C. Lim, Y. Kim, J. Barnett, G. Bersuker, G. A. Brown, C. D. Young, P. M. Zeitzoff, J. Gutt, P. Lysaght, M. I. ...
PWmat在IEDM2018发表关于high-k gate stacks的重要研究成果 近日,中科院半导体所姜向伟副研究员课题组用PWmat研究了high-k闸极堆叠层中空穴捕获过程,采用DFT与Marcus理论结合研究整个闸极堆叠层界面处的空穴捕获过程。文中研究了Si通道、SiO2界面和HfO2组成的high-k闸极堆叠层,首次提出一种直接计算该堆叠层界面处空穴捕...
Work function adjustment in high-k gate stacks including gate dielectrics of different thicknessUS20110049642 * Aug 2, 2010 Mar 3, 2011 Thilo Scheiper Work function adjustment in high-k gate stacks including gate dielectrics of different thickness...
The gate stack should be regarded as a multi-element interfacial layered structure wherein the high-k gate dielectric and gate electrodes (and their corresponding interfaces) must be successfully comprehended. The surface clean and subsequent surface conditioning prior to high-k deposition as well as...
The present invention relates generally to formation of high-K gate stacks in semiconductor devices. More particularly, methods are provided for formation of high-K gate stacks for MOSFET devices so as to control the MOSFET threshold voltage. Preferred embodiments provide threshold voltage control in ...
HIGH-k DIELECTRICS IN GATE STACK As the gate length shrinks in the technology node, the gate oxide leakage current increases with decreasing SiO2 thickness. The use of SiO2 in gate stacks is limited by already approximately one monolayer . High-k dielectrics such as HfO2, offer a thicker oxide...
Physics of hole trapping process in high-k gate stacks: A direct simulation formalism for the whole interface system combining density-functional theory an... Physics of hole trapping process in high-k gate stacks: A direct simulation formalism for the whole interface system combining density-...
We have developed a process for forming an ultra-thin HfSiO_x interfacial layer (HfSiO_x-IL) for high-k gate stacks. The HfSiO_x-IL was grown by the solid-phase reaction between HfO_2 and Si-substrate performed by repeating the sequence of ALD HfO_2 deposition and RTA. The HfSiO_...
STRUCTURE AND METHOD TO MINIMIZE REGROWTH AND WORK FUNCTION SHIFT IN HIGH-K GATE STACKS United States Patent Application 20110062546 Kind Code: A1 Abstract: The present invention provides a semiconductor structure comprising high-k material portions that are self-aligned with respect to the active ...
United States Patent US8916433 Note: If you have problems viewing the PDF, please make sure you have the latest version ofAdobe Acrobat. Back to full text