High-level vs. RTL combinational equivalence: An introduction - Hu - 2006 () Citation Context ...TL and gate-level hardware designs [4, 17]. Research has also be done on combinational equivalence checking between high-level designs in software-like languages (e.g., SystemC) and RTL-level...
(3) The equivalence between C and synthesized RTL models was difficult to prove “formally”. RTL synthesis adoption accelerated in tandem with the use of (combinational) logic cone equivalency checking (LEC) tools, using the correspondence mapping between RTL and gate-level state points – there ...
There has always been talk in the industry to have a single model which can be used in virtual prototypes, and also synthesized using a HLS tool to generate RTL. However both use-cases require different kinds of high level code. HLS requires code which is compliant with the synthesizable...
A method for the fully automatic equivalence verification of a design before and after the scheduling step of high-level synthesis is presented. The techni... H Eveking,H Hinrichsen,G Ritter - Design, Automation & Test in Europe Conference & Exhibition 被引量: 65发表: 1999年 Collection of ...
High-Level vs. RTL Combinational Equivalence: An Introduction In this paper, we focus on fast solvers with linearithmic complexity in space for high-dimensional time-fractional subdiffusion equations. Firstly, we pres... A Hu - 《Journal of Computational Physics》 被引量: 19发表: 2006年 Develop...
Objects may include a reference to relevant lines of source RTL code. A graphical user interface ( GUI ) displays the RTL code in an ... COILEY MARK A. - US 被引量: 34发表: 2006年 Efficient equivalence checking of multi-phase designs using retiming Banerjee, “Efficient equivalence ...
When that is done, logic synthesis is applied to transform the RTL to gates, and the resulting system model is verified using either simulation or formal equivalence methods. It is important to note that a gate level simulation uses the same test bench as the RTL simulation. In a system ...
In this paper, we present a two-step approach, embodied in two equivalence checking tools, VERIFOX and HW-CBMC, to validate designs at the software and RTL levels, respectively. VERIFOX is used for equivalence checking of an untimed software model in C against a high-level reference model ...
=-=[9]-=- propose the use of bisimulation correspondence to validate designs generated by behavioral synthesis. However, neither approach provides pipelining-specific equivalence checking strategies that effec...S. Kundu, S. Lerner, and R. Gupta. Validating high-level synthe- sis. In Proceedings ...
Equivalence checkingHigh-level specificationInterface protocolRTL designDigital application complexity has steadily made it harder to discover and debug behavioral inconsistencies at register transfer level (RTL). Aiming to bring a solution, several techniques have appeared as alternatives to verify that a ...