“A Capacitorless Double Gate DRAM Technology for Sub-100-nm Embedded and Stand-Alone Memory Applications, IEEE Transactions on Electron Devices”, vol. 50, No. 12, Dec. 2003, pp. 2408-2416. Charles Kuo et al., “A Capacitorless Double-Gate DRAM Cell Design for High Density Applications...
an effective number of bits of 18.8 bits; a harmonic distortion of −110 dB in the signal bandwidth; an output background noise of −141 dB; the design of reference voltage is 2.5 V, so that the signal Mbiacnrodmwachidintehs 2e0q1u8,iv9,a1l2e1nt input noise voltage density is 198...