the problem doesn't seem related to VHDL support in my view. You can neither send a hexadecimal literal to a numerical Verilog module parameter. Only decimal numbers seem to be accepted as block parameters for numerical values. Translate 0 Kudos Copy link Reply pertrl Beginner 12...
Still, I`m getting zero values for addresses 0x08 - 0x0F, while actual content of these are shifted to 0x10 - 0x18, exactly the way it was simulated. This gap is inserted after every 8-word blocks of data and always consists of 8 words of zeros. So, obviously there is ...