I use GPIO_AD_xx as FlexIO to output 60MHz in PFM mode. The waveform is no problem when there is no load, but the waveform becomes unacceptably bad once connecting some logic gate ICs. I think if the drive strength of the GPIO becomes higher, this issue will be solved. Q1 If I ...
The drive strength of an output is configured via the IO mux ("FUN_DRV"). As every signal must pass through the IO mux, whether it's GPIO, peripheral-direct, or peripheral via GPIO matrix, it seems that drive strength (as well as pull-up/down) can be set independent of the signal...
Drive strength is the current that a GPIO will try to drive. It is usually specified inmA. Specifying a too large value at the system level can cause the CPU to drive too much total current, which can burn it. Specifying a too low value can burn the GPIO itself. It is important to ...
aThe GPIOCTRL register control pull-up for each individual GPIO pin, extra drive strength for all pins and analog function for pin 0 and 1. GPIOCTRL定位控制器为每个单独GPIO别针、额外推进力量为所有别针和模式作用拉扯为别针0和1。[translate]...
PMOS管测试步骤(Drive High Ability) 1、将IO PAD配置成output模式,DUT供电电压为可正常工作的最低电压,如依datasheet允许,下降10%(3.3V——>2.97V)等。 2、将IO PAD配置成最大Driving电流(Idrv-max)模式,例如,如果PAD driving能力有4/8 mA两档,则应该选择8mA这档进行测试。
So just to be clear, does this means that even if I connect 3.3V supply directly to I/O pin and set the pin as output and drive it as low (or vice versa i.e. connect GND to I/O pin and drive it high), the amount of current that will flow will ...
Now the drive strength (current source & sink capability) of GPIO pin is based on the value configured for DSE field of the register as shown in below picture: So from this, Q1: If DSE is 001 and VDD is 3.3V then the current I can source or sink ...