PALO ALTO, Calif. – Tensilica described a new integer DSP core for next-generation cellular applications that when made in a 28nm process can compute 100 GMACs/second at less than a Watt. The BBE64 core is a new instruction set architecture based on the companies' currentXtensa LX4 core. ...
International Symposium on Low Power Electronics and DesignHe, X., Jin, X., Wang, M., Zhou, D., Goto, S.: A 98 GMACs/W 32-core vector processor in 65 nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. E94-A(12), 2609- 2618 (2011)...
A prototype chip of DAP with 256 cores is fabricated in a 12-nm FINFET process and has been verified. The measurement results show that DAP achieves 507 GMACs/J and a peak performance of 264 GMACs. 展开 关键词: Kernel Wireless communication Parallel processing Systolic arrays Registers ...