Genetic-Algorithm-based Test Pattern Generation for Crosstalk Faults between On-Chip Aggressor and VictimCrosstalkgenetic algorithmsATPGWith the shrinking feature size and increasing aspect ratios of interconnects in DSM chips, the coupling noise between adjacent interconnects has become a major signal ...
In this paper, we propose a Genetic Algorithm (GA) based Automatic Test Pattern Generation (ATPG) technique, enhanced by automated solution to an associated Boolean Satisfiability problem. The main insight is that given a specific internal trigger condition, it is not possible to attack an ...
Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits An efficient automatic test pattern generator for I/sub DDQ/ current testing of CMOS digital circuits is presented. The complete two-line bridging fault se... T Lee,IN Hajj,EM Rudnick,... - ...
(i.e., to output ports or to memory selecting macros based on the experience gathered locations).during previous activations; a Genetic Algorithmmplements the latter. As an example, the macro for any arithmeticnstruction is composed of three phases:The pseudo-code of the search algorithm we ...
In this paper, we propose a Genetic Algorithm (GA) based Automatic Test Pattern Generation (ATPG) technique, enhanced by automated solution to an associated Boolean Satisfiability problem. The main insight is that given a specific internal trigger condition, it is not possible to attack an ...
Rodriguez, "A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms", Proc. International Test Conference, pp. 286-293, 1996.P. Girard, G. Landrault, S. Pravossoudovitch, and B. Rodriguez, "A Diagnostic ATPG for Delay Faults based on Genetic Algorithm," in Proc. IEEE Int. Test...
ATPG for Crosstalk Delay Faults Using Multi-objective Genetic AlgorithmPower consumption and delay are two of the most important design criteria in today's deep submicron VLSI technology. Energy dissipation has become a major concern in today's VLSI technology with increasing use of wireless ...
Parallel genetic algorithm for automatic generation of test sequences for digital circuits. In the Proc. Int. Conf. and Exhibition HPCN EUROPE, pp. 454-459, April 1996.Corno, F., Prinetto, P., Rebaudengo, M., and Reorda, M. S. (1996). A Parallel Genetic Algorithm for Automatic ...
A parallel technique for ATPG using genetic algorithmsThis paper presents a new technique for test pattern generation based on a genetic algorithm and parallel processing techniques. This new method offers compact test sets, compared to other methods, that achieve maximum coverage.Sabry...
A genetic algorithm for the computation of initialization sequences for synchronous sequential circuitsTesting circuits which do not include a global reset signal requires either complex ATPG algorithms based on 9- or even 256-valued algebras, or some suitable method to generate initialization sequences...