• The processor controls voltage ramp rates internally to ensure glitch-free transitions. Because there is low transition latency between P-states, a significant number of transitions per-second are possible. 34 Datasheet, Volume 1 of 2 Technologies 2.4.8 2.4.9 Note: 2.4.10 Intel® ...
033 Problem Implication Workaround Status Processor DDR VREF Signals May Briefly Exceed JEDEC Spec When Entering S3 State Voltage glitch of up to 200mV on the VREF signal lasting for about 1mS may be observed when entering System S3 state. This violates the JEDEC DDR specifications. Inte...
089 Problem Implication Workaround Status Potential Partial Trace Data Loss in Intel® Trace Hub ODLA When Storing to Memory When Intel® Trace Hub's On-Die Logic Analyzer (ODLA) is configured to trace to memory, under complex microarchitectural conditions, the trace may lose a timestamp....