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Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from 2.4 V and down to 1.8V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it...
PDR_ON C6 H3 143 - - P - Default: PDR_ON VDD C5 C4 144 100 64 P - Default: VDD PI4 D4 - - - - I/O 5VT Default: PI4 Alternate:TIMER7_BRKIN,EXMC_NBL2,DCI_D5, EVENTOUT PI5 C4 - - - - I/O 5VT Default: PI5 Alternate:TIMER7_CH0,EXMC_NBL...
POR/PDR上电/掉电复位用于检测VDD电压低于特定阈值时产生复位信号,复位除备份域之外的整个芯片。如下表图,上电时VDD电压从低到高上升,超过VPOR且超过VHYST时间后,触发POR。当掉电时VDD电压从高到低下降,超过VPDR时,触发PDR。从图中可以看出一般VPOR比VPDR电压高50mv。
Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from/down to 2.6 V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the ...
(1) GD32F450xx Functions description Default: PE1 PE1 A3 142 98 I/O 5VT Alternate: TIMER0_CH1_ON, UART7_TX, EXMC_NBL1, DCI_D3, EVENTOUT VSS D5 - 99 P - Default: VSS PDR_ON C6 143 - P - Default: PDR_ON VDD C5 144 100 P - Default: VDD PI4 D4 - - I/O 5VT ...
and external 32.768 KHz crystal oscillator Integrated system clock PLL 2.6 to 3.6 V application supply and I/Os Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD) The Clock Control Unit (CCU) provides a range of oscillator and clock functions. ...
(1) GD32F450xx Functions description Default: PE1 PE1 A3 142 98 I/O 5VT Alternate: TIMER0_CH1_ON, UART7_TX, EXMC_NBL1, DCI_D3, EVENTOUT VSS D5 - 99 P - Default: VSS PDR_ON C6 143 - P - Default: PDR_ON VDD C5 144 100 P - Default: VDD PI4 D4 - - I/O 5VT ...
POR/PDR 上电/掉电复位用于检测VDD电压低于特定阈值时产生复位信号,复位除备份域之外的整个芯片。如下表图, 上电时VDD电压从低到高上升,超过VPOR且超过VHYST时间后,触发POR。 当掉电时VDD电压从高到低下降,超过VPDR时,触发PDR。 从图中可以看出一般VPOR比VPDR电压高50mv。 LDO 用于将VDD电压降到1.2V为1.2...