PDR_ON C6 H3 143 - - P - Default: PDR_ON VDD C5 C4 144 100 64 P - Default: VDD PI4 D4 - - - - I/O 5VT Default: PI4 Alternate:TIMER7_BRKIN,EXMC_NBL2,DCI_D5, EVENTOUT PI5 C4 - - - - I/O 5VT Default: PI5 Alternate:TIMER7_CH0,EXMC_NBL...
Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from 2.4 V and down to 1.8V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it...
PDR_ON143P-Default:PDR_ON(3) VDD144P-Default:VDD Notes: (1)Type:I=input,O=output,P=power. (2)I/OLevel:5VT=5Vtolerant. (3)PDR_ONpinshouldbepulleduptoVDD,refertoFigure4-2.RecommendedPDR_ON pincircuit. 2.6.4.GD32F527VxLQFP100pindefinitions Table2-7.GD32F527VxLQFP100pindefinitions ...
POR/PDR上电/掉电复位用于检测VDD电压低于特定阈值时产生复位信号,复位除备份域之外的整个芯片。如下表图,上电时VDD电压从低到高上升,超过VPOR且超过VHYST时间后,触发POR。 当掉电时VDD电压从高到低下降,超过VPDR时,触发PDR。 从图中可以看出一般VPOR比VPDR电压高50mv。
31 GD32F130xx Datasheet Integrated system clock PLL 2.6 to 3.6 V application supply and I/Os Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD) The Clock Control Unit (CCU) provides a range of oscillator and clock functions. ...
POR/PDR 上电/掉电复位用于检测VDD电压低于特定阈值时产生复位信号,复位除备份域之外的整个芯片。如下表图, 上电时VDD电压从低到高上升,超过VPOR且超过VHYST时间后,触发POR。 当掉电时VDD电压从高到低下降,超过VPDR时,触发PDR。 从图中可以看出一般VPOR比VPDR电压高50mv。 LDO 用于将VDD电压降到1.2V为1.2...
Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from/down to 2.6 V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the ...
On-chip memory32 3.3 Clock, reset and supply management 33 3.4 Boot modes34 3.5 Power saving modes 34 3.6 Analog to digital converter (ADC) 35 3.7 Digital to analog converter (DAC)35 3.8 DMA 36 3.9 General-purpose inputs/outputs (GPIOs)36 3.10 Timers and PWM generation37 3.11 Real time...
TIMER0_CH1_ON, EXMC_NBL1, DCI_D3, EVENTOUT VSS D5 P - Default: VSS PDR_ON C6 P - Default: PDR_ON VDD C5 P - Default: VDD Default: PI4 PI4 D4 I/O 5VT Alternate: TIMER7_BRKIN, EXMC_NBL2, DCI_D5, EVENTOUT Default: PI5 PI5 C4 I/O 5VT Alternate: TIMER7_CH0, EXMC_NB...
提供LED on/off接口 #defineDRV_LED1GPIOC,GPIO_PIN_0#defineDRV_LED2GPIOC,GPIO_PIN_2#defineDRV_LED3GPIOE,GPIO_PIN_0#defineDRV_LED4GPIOE,GPIO_PIN_1#defineDRV_LED_On(led) GPIO_SetBits(led);#defineDRV_LED_Off(led) GPIO_ResetBits(led);externvoidDRV_LED_Init(void); ...