The gate-source control unit comprise an asymmetric transient voltage suppressor (TVS) diode (8) or two Zener diodes (10, 10') or one or more avalanche diodes arranged between the gate terminal (G) and the source terminal (S) of the semiconductor switch (4).APPEL, TOBIAS...
The first phase during turn-ON is the preboost phase and lasts for 135ns according to Figure 3. The preboost charges the gate-emitter voltage to a value below the gate-emitter threshold voltage Vge(th). The current during the preboost phase depends on the gate charge and is theref...
A switch mode regulator circuit is provided to facilitate the conversion from one voltage level to another in a substantially power lossless manner. The circuit is particularly advantageous in instances where the power supply can be operable in a discontinuous mode, as inductor-capacitor oscillatory t...
Research on Current Injection Active Drive Method of SiC MOSFET With Transient Voltage and Current Spike and Oscillation Suppression In order to meet the requirements of high frequency, high efficiency and high power density of power electronic systems, SiC MOSFETs are increasingly used ... C Feng,...
A 1-MHz high-efficiency 12-V Buck voltage... Z Zhang,YF Liu - US 被引量: 48发表: 2010年 Current-source gate driver C. Sen, "A 1-MHz high-efficiency 12-V buck voltage regulator with a new current-source gate driver," IEEE Trans. on Power Electron., Vol. 23, No. 6, pp. ...
关键词: Logic gates Insulated gate bipolar transistors Voltage control Switches Transient analysis Switching loss DOI: 10.1109/TPEL.2016.2587340 被引量: 3 年份: 2017 收藏 引用 批量引用 报错 分享 全部来源 免费下载 求助全文 国家科技图书文献中心 (权威机构) IEEEXplore IEEEXplore (全网免费下载) 掌桥...
Due to the inherent floating body effect in the FD-SOI transistor, charge accumulation in the silicon thin film becomes inevitable when the gate-to-source voltage (V_) is smaller than the flat-band voltage (V_). In order to eliminate the transient leakage current problem in p^+-poly gate...
rather it is only activated by a sustained signal and only operates during the duration of the signal. Therefore, a noise spike or other typical transient would not activate the level triggered logic 110. The level-triggered logic 110 may be implemented as serial inverters. The serial inverters...
The upper end of this range is driven by the 20-V absolute maximum voltage rating of the VDD pin of the device (which is a stress rating). Keeping a 2-V margin to allow for transient voltage spikes, the maximum recommended voltage for the VDD pin is 18 V. The UVLO protection feature...
voltage • 8-V (B) or 12-V VCC UVLO Options • Rail-to-rail output • 105-ns (maximum) propagation delay • 25-ns (maximum) part-to-part delay matching • 35-ns (maximum) pulse width distortion • 150-kV/μs (minimum) common-mode transient immunity (CMTI) • Isolation...