pinctrl_lsio_pwm3: lsio_pwm3_grp {fsl,pins = <IMX8QXP_UART1_CTS_B_LSIO_PWM3_OUT 0xC8000020>;}; Thank you-- Peter Solved! Go to Solution. Labels: i.MX 8 Family | i.MX 8QuadMax (8QM) | 8QuadPlus Tags: lsio_pwm 0...
fsl_esdhc: Add device tree fixups Browse files This patch implements fdt_fixup_esdhc() function that is used to fixup the device tree. The function adds status = "disabled" propery if esdhc pins muxed away, otherwise it fixups clock-frequency for esdhc nodes. Signed-off-by: Anton ...
In our case, I think you don't need to add the "pinctrl-1" and "sleep" in your device tree file. The 0x0 value is the PAD Ctrl setting of the pins. I think you can refer to this one. fsl-imx8qxp-lpddr4-arm2-lpspi.dts\freescale\dts\boot\arm64\arch - linux-...
- GPIO Support: CONFIG_PCA953X - use NXP's PCA953X series I2C GPIO The CONFIG_SYS_I2C_PCA953X_WIDTH option specifies a list of chip-ngpio pairs that tell the PCA953X driver the number of pins supported by a particular chip. Note that if the GPIO device uses I2C, then the I2C ...
> fsl,pins = < > MX6QDL_PAD_ENET_MDIO__ENET_MDIO > 0x1b0b0 > MX6QDL_PAD_ENET_MDC__ENET_MDC > 0x1b0b0 > MX6QDL_PAD_RGMII_TXC__RGMII_TXC > 0x1b030 > MX6QDL_PAD_RGMII_TD0__RGMII_TD0 > 0x1b030 > MX6QDL_PAD_RGMII_TD1__RGMII_TD1 ...
/* invert AQR105 IRQ pins polarity */ out_be32(&scfg->intpcr, AQR105_IRQ_MASK); return 0; } Expand Down 2 changes: 1 addition & 1 deletion 2 board/freescale/ls2080aqds/MAINTAINERS Show comments View file Edit file Delete file This file contains bidirectional Unicode text that ...