esdhc_clock_control(priv, false); esdhc_setbits32(®s->esdhcctl, ESDHCCTL_PCS); esdhc_clock_control(priv, true); }/* Set the clock speed */ if (priv->clock != mmc->clock) set_sysctl(priv, mmc, mmc->clock); @@ -779,6 +779,8 @@ int fsl_esdhc_initialize(bd_t *bis...
return esdhc_initialize(bis); } void fdt_fixup_esdhc(void *blob, bd_t *bd) { const char *compat = "fsl,esdhc"; const char *status = "okay"; if (!hwconfig("esdhc")) { status = "disabled"; goto out; } do_fixup_by_compat_u32(blob, compat, "clock-frequency", gd->sdhc_...
3 changes: 3 additions & 0 deletions 3 drivers/mmc/fsl_esdhc.c Original file line numberDiff line numberDiff line change @@ -543,6 +543,9 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) /* First reset the eSDHC controller */ esdhc_reset(regs);...
int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg); void fdt_fixup_esdhc(void *blob, struct bd_info *bd); #else static inline int fsl_esdhc_mmc_init(struct bd_info *bis) { return -ENOSYS; } static inline void fdt_fixup_esdhc(void *blob, str...
struct fsl_esdhc_cfg esdhc_cfg[2] = { {MMC_SDHC1_BASE_ADDR, 1}, {MMC_SDHC2_BASE_ADDR, 1}, {MMC_SDHC1_BASE_ADDR}, {MMC_SDHC2_BASE_ADDR}, }; #endif4 changes: 2 additions & 2 deletions 4 board/freescale/mx53ard/mx53ard.c Original file line numberDiff line numberDiff line...
val &= ~ESDHC_TUNING_STEP_MASK; val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;/* Disable the CMD CRC check for tuning, if not, need to * add some delay after every tuning command, because * hardware standard tuning logic will directly go to next ...
esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, @@ -722,7 +718,6 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); priv->sdhc_clk = cfg->sdhc_clk;...
#if defined CONFIG_SYS_FSL_ESDHC_LE #define esdhc_read32 in_le32 #define esdhc_write32 out_le32 #define esdhc_clrsetbits32 clrsetbits_le32 #define esdhc_clrbits32 clrbits_le32 #define esdhc_setbits32 setbits_le32 #elif defined(CONFIG_SYS_FSL_ESDHC_BE) #define esdhc_read32 in...
For LS102xA, the processor is in little-endian mode, while esdhc IP is in big-endian mode. CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE are added. So accessing ESDHC registers can be determined by ESDHC IP's endian mode. Signed-off-by: Alison Wang <alison.wang@freescale....
>> MMC_SDHCI_OF_ESDHC >> >> [...] >> >> >> >> >> And I think stubs for reading SVR is quite a bad idea. It'll make >> >> the driver build but it will silently not be able to apply SVR-based >> workarounds. >> > >> > It doesn't have to be "silent", the dr...