An object of the present invention is to obtain a frequency division circuit including a flip-flop circuit capable of low-voltage and high-frequency operation. The frequency division circuit has bipolar transistors and MOS transistors. Thus, the circuit includes transistors that are connected to the...
专利名称：FLIP-FLOP CIRCUIT, FREQUENCY DIVIDER USING FLIP-FLOP CIRCUIT, AND COMMUNICATION APPARATUS OR ELECTRONIC EQUIPMENT USING FREQUENCY DIVIDER 发明人：YAMAMOTO KEN,山本 憲 申请号：JP2008089985 申请日：20080331 公开号：JP2009246639A 公开日：20091022 专利内容由知识产权出版社提供 专利附图：
Frequency divider, a phase lock oscillator and a flip-flop circuit using the frequency divider A frequency divider comprises first and second basic gates. Each basic gate includes first and second differential circuits, an adder unit for adding outputs from the first and second differential circuits...
FLIP-FLOP CIRCUIT, FREQUENCY DIVIDER USING FLIP-FLOP CIRCUIT, AND COMMUNICATION APPARATUS OR ELECTRONIC EQUIPMENT USING FREQUENCY DIVIDER 来自 百度文库 喜欢 0 阅读量: 19 申请(专利)号: JP20080089985 申请日期: 2008-03-31 公开/公告号: JP2009246639A 公开/公告日期: 2009-10-22 ...
A flip-flop, and a frequency divider and an RF circuit using the flip-flop. The frequency divider, which receives a first signal and generates a second signal by dividing a frequency of the first signal, including a plurality of flip-flops that each latch and output a signal based on the...
3. A device as claimed in claim 1, characterized in that said frequency multiplier circuit is realized in current mode logic. 4. A device as claimed in claim 1, characterized in that the frequency divider circuit includes first and second flip-flops having flip-flop inputs and whose states ...
A frequency multiplier design that uses a flip-flop to output (1) a first edge on an output clock signal upon receipt of a first transition of an input clock signal and (2) a second edge on the output clock signal before receipt of a second transition of the input clock signal is prov...
According to the frequency multiplier of the present invention, an output clock signal of multiplied frequency is emitted from an exclusive NOR circuit which enters an input clock signal and a signal obtained by delaying the input clock signal via a first delay circuit. To the first delay circuit...
CIRCUIT ARRANGEMENT Upon interception of a signal the output of gate 12 becomes high, transistor 22 is cut off and the tuning again controlled by discriminator 24. Hysteresis circuit 10.-The two controlling inputs of a bistable flip-flop 35, Fig. 2... G Roosen 被引量: 0发表: 1973年 Ci...
Figure 6 shows measurement results on how a self-oscillation frequency of a frequency divider comprising a latch circuit changes when using a temperature-dependent tuning voltage. Figure 7 schematically shows a flip-flop based frequency divider in which two latches are utilized. ...