PUDC_B引脚：影响上电后，以及在FPGA配置过程中IO脚的状态。必须在设计时上拉或者下拉，配置程序时不能悬空。FPGA是个芯片，没有rdsig这种引脚。估计是在某种硬件描述语言中，设计者声明的信号名称，看起来像是“读信号”的意思（read_signal）。
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PUDC_B管脚用途 Pull-Up During Configuration (bar) Active-Low PUDC_B input enables internal pull-up resistors on the SelectIO pins after power-up and during configuration. • When PUDC_B is Low, internal pull-up resistors are enabled on each SelectIO pin. • When PUDC_B is High, intern...
PUDC_B管脚用途 Pull-Up During Configuration (bar) Active-Low PUDC_B input enables internal pull-up resistors on the SelectIO pins after power-up and during configuration. • When PUDC_B is Low, internal pull-up resistors are enabled on each SelectIO pin. • When PUDC_B is High, intern...
• When PUDC_B is High, internal pull-up resistors are disabled on each SelectIO pin. PUDC_B must be tied either directly, or via a ≤ 1kΩ to VCCO_14 or GND. Caution! Do not allow this pin to float before and during configuration. ...